In a ferroelectric memory, plural pieces of memory cells are arranged in a matrix form, and each one of the memory cells is provided with a ferroelectric capacitor. Further, the ferroelectric capacitors are divided into those of a stack type and those of a planar type, of which the planar-type ferroelectric capacitor sometimes has a plate line commonly used for a group of top electrodes in plural lines.
FIGS. 10A and 10B to FIGS. 13A and 13B are views showing a conventional method for fabricating a ferroelectric capacitor in the order of steps. Here, the FIGS. 10A, 11A, 12A, and 13A are top views, and FIGS. 10B, 11B, 12B, and 13B are sectional views taken along the I—I line in FIGS. 10A, 11A, 12A, and 13A, respectively.
In the conventional fabricating method, first, field-effect transistors (not shown) are formed on a semiconductor substrate (not shown). Next, an interlayer insulation film 101 covering respective transistors are formed. Next, as shown in FIGS. 10A and 10B, a bottom electrode film (material film for a bottom electrode) 103, a ferroelectric film 104, and a top electrode film (material film for a top electrode) 105 are sequentially formed on the interlayer insulation film 101. After that, the same number of resist masks 111 intended for etching a top electrode as of the top electrodes to be formed are formed on the top electrode film 105. At this time, the shapes of the resist masks 111 intended for etching a top electrode are made to match with the design planar shapes (rectangle) of the individual top electrodes. However, at the time of a photography to form the resist masks 111, the four corners of the respective resist masks 111 are curved due to a lack of contrast, as shown in FIG. 10A.
Subsequently, the top electrode film 105 is patterned using the resist masks 111 intended for etching a top electrode, and the resist masks 111 intended for etching a top electrode are removed thereafter.
Next, a resist mask (not shown) intended for etching a ferroelectric film is formed on the top electrode film 105. Then, the ferroelectric film 104 is etched using the resist mask intended for etching a ferroelectric film, and the resist mask intended for etching a ferroelectric film is removed thereafter, as shown in FIGS. 12A and 12B.
Subsequently, as shown in FIGS. 13A and 13B, a resist mask 112 intended for etching a bottom electrode is formed on the top electrode film 105, the ferroelectric film 104, and the bottom electrode film 103. Then, the bottom electrode 103 is etched using the resist mask 112 intended for etching a bottom electrode, and the resist mask 112 intended for etching a bottom electrode is removed thereafter, as shown in FIGS. 14A and 14B.
The ferroelectric capacitor is thus fabricated.
However, in such a conventional fabricating method, as described above, there are generated curbed portions at the four corners of the resist mask 111 intended for etching a top electrode, causing the top electrode to be small as compared to the design value. For instance, when the resist mask 111 intended for etching a top electrode is made from an i-ray resist having a square of a 1 μm side, then the pattern becomes smaller than the design value by approximately 10%. Such a loss of area becomes remarkable as the integration degree is improved to thereby downsize the top electrode in the future, so that the loss results in an obstacle to improve the integration degree.
(Patent Document 1)
Japanese Patent Application Laid-Open No. 2002-009256.